Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes spacers 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacers 122 are comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacers 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET 100, including the channel length of the MOSFET 100, are scaled down further, the depth of the drain and source extension junctions 104 and 106 are desired to be shallower for minimizing undesired short channel effects of the MOSFET 100, as known to one of ordinary skill in the art of integrated circuit fabrication. However, a shallower depth for the drain and source extension junctions 104 and 106 typically results in higher sheet resistance at the drain and source extension junctions 104 and 106. Such higher parasitic resistance at the drain and source of the MOSFET 100 undesirably slows down the speed performance of the MOSFET 100. Thus, a mechanism is desired for fabricating the drain and source extension junctions 104 and 106 with minimized depth but also with minimized sheet resistance.
Furthermore, as the dimensions of the MOSFET 100 are scaled down further, the thickness of the gate dielectric 116 is also further scaled down for achieving a desired threshold voltage. However, a thinner gate dielectric 116 results in undesired leakage current through the gate of the MOSFET 100 from charge carrier tunneling through such a thin gate dielectric 116. A high-K dielectric material with a dielectric constant higher than that of silicon dioxide (SiO2) is used instead of silicon dioxide (SiO2) for the gate dielectric 116. Such a gate dielectric 116 comprised of a high-K dielectric material is formed with higher thickness than if the gate dielectric 116 were comprised of silicon dioxide (SiO2) for attaining a given threshold voltage.
Such a higher thickness of the gate dielectric 116 comprised of a high-K dielectric material minimizes undesired leakage current through the gate of the MOSFET 100 from charge carrier tunneling through the gate dielectric 116. However, high-K dielectric materials tend to be thermally unstable at relatively high temperatures greater than about 950° Celsius. Thus, low thermal anneal processes are desired for activating the dopant within the drain and source extension junctions 104 and 106 and within the drain and source contact junctions 108 and 112 for preserving integrity of the gate dielectric 116 comprised of a high-K dielectric material.